The present invention relates to the field of electronic circuitry, and in particular to multi-layer circuit assemblies such as chip scale packages, and the preparation thereof.
An electronic circuit package, or assembly, comprises many individual components including, for example, resistors, transistors, capacitors, etc. These components are interconnected to form circuits, and circuits are likewise interconnected to form units having specific functions. In microelectronic circuit packages, circuits and units are prepared in packaging levels of increasing scale. The smallest scale packaging levels are typically semiconductor chips housing multiple microcircuits and/or other components. Such chips are usually made from ceramics, silicon, and the like. Intermediate package levels (xe2x80x9cchip carriersxe2x80x9d) comprising multi-layer substrates may have attached thereto a plurality of small-scale chips housing many microelectronic circuits. In turn, these intermediate package levels are themselves attached to larger scale circuit cards, motherboards, and the like. The intermediate package levels serve several purposes in the circuit assembly including structural support, transitional integration of the smaller scale microcircuits and circuits to larger scale boards, and the dissipation of heat from the circuit assembly.
Substrates used in conventional intermediate package levels have included ceramic, fiberglass reinforced polyepoxides, and polyimides. These substrates, while offering sufficient rigidity to provide structural support to the circuit assembly, typically have thermal coefficients of expansion much different than that of the microelectronic chips being attached thereto. As a result, failure of the circuit assembly after repeated use is a risk due to failure of adhesive joints between the layers of the assembly.
Likewise, dielectric materials used on the substrates must meet several requirements, including conformality and flame resistance. Moreover, as circuit packages are being designed to operate at ever higher frequencies, dielectric materials must be highly effective (i.e., they must have dielectric constants as low as possible that do not degrade) in order to prevent crosstalk in the package. Conventional dielectrics include polyimides, polyepoxides, phenolics, and fluorocarbons.
U.S. Pat. Nos. 5,224,265 and 5,232,548 disclose methods of fabricating multi-layer thin-film wiring structures for use in circuit assemblies. The dielectric applied to the core substrate is preferably a fully cured and annealed thermoplastic polymer such as polytetrafluoroethylene, polysulfone, or polyimide-siloxane, preferably applied by lamination. Such dielectrics are not necessarily applied as conformal coatings, and may not have dielectric constants or dissipation factors low enough to accommodate the high frequencies of circuit systems currently being designed for the electronics market today. Moreover, dielectric properties of conventional dielectric coatings have been known to degrade at high frequencies. Additionally, while the references disclose through holes (xe2x80x9cviasxe2x80x9d) in the wiring structures, there is no appreciation in the references of the need for a relatively high via density. High via density allows for a high number of chip connections, as may be required in a highly functional chip scale package for applications such as cellular phones and the like.
It should be noted that high via density in a circuit layer is critical for the operation of a circuit system having a high number of chip connections; however, high via density also contributes to crosstalk. Therefore, a circuit package designed with high via density needs to be fabricated using a very effective dielectric that does not degrade at high frequencies.
U.S. Pat. No. 5,153,986 discloses a method of fabricating metal core layers for a multi-layer circuit board. Suitable dielectrics include vapor-depositable conformal polymeric coatings. The method uses solid metal cores and the reference describes in broad, generic terms circuitization of the substrate. Circuitization of intermediate package levels is conventionally performed by applying a positive- or negative-acting photoresist to the metallized substrate, followed by exposure, development, and stripping to yield a desired circuit pattern. Photoresist compositions are typically applied by laminating, spraying, or immersion. The photoresist layer thus applied may have a thickness of 5 microns to 50 microns.
In addition to the ceramic, fiberglass reinforced polyepoxides, and polyimides mentioned above, conventional substrates used in intermediate package levels further include solid metal sheets such as are disclosed in U.S. Pat. No. 5,153,986. These solid substrates must be perforated during fabrication of the circuit assembly to provide through holes for alignment purposes. Again, while the reference discloses vias in the circuit layers, there is no appreciation of the need for a relatively high via density to accommodate highly functionalized chips.
In view of the prior art processes, it would be desirable to provide a process for preparing a multi-layer circuit assembly that overcomes the drawbacks of the prior art. That is, it would be desirable to provide a process for preparing a multi-layer circuit assembly with high via density to accommodate highly functional components, using a very effective dielectric that does not degrade at high frequencies and meets further requirements including conformality and flame resistance.
It is an object of the present invention to provide a multi-layer circuit assembly and a process for preparing it, such that the final assembly comprises component layers having thermal coefficients of expansion that are compatible with those of smaller and larger scale components which may be attached to the circuit assembly.
It is a further object of the present invention to provide high via density, allowing for more electrical interconnects from highly functional chips to level two packages.
Additional objects of the present invention include superior dielectric performance and fine line resolution to provide for advanced chip attachment techniques.
In accordance with the present invention, a process for fabricating a multi-layer circuit assembly is provided comprising the following steps:
(a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
(b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core;
(c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core;
(d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and
(e) applying a resinous photosensitive layer to the metal layer.
Also provided is a multi-layer circuit assembly prepared by the process of the present invention, comprising:
(a) a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
(b) a dielectric coating applied onto all exposed surfaces of the electrically conductive core, and ablated in a predetermined pattern to expose sections of the electrically conductive core;
(c) a layer of metal applied to all surfaces, thereby forming metallized vias through the electrically conductive core; and
(d) a resinous photosensitive layer applied to the metal layer.